1. Technical Field
The present invention relates to a semiconductor cell including a fin-type buried gate and a method of manufacturing the same.
2. Related Art
Most electric appliances include semiconductor devices. Semiconductor devices include electric elements such as transistors, resistors, capacitors and the like. The electric elements are designed to perform partial functions of the electric appliances and are integrated on a semiconductor substrate. For example, electronic appliances such as computers or digital cameras include memory chips for storing information and processing chips for controlling the information. The memory chips and processing chips include electric elements integrated on the semiconductor substrate.
On the other hand, semiconductor devices need to be more highly integrated to satisfy user demands for good performance and low price. As the integration degree of semiconductor devices increases, the design rule is scaled down and patterns of the semiconductor devices become fine. With extra miniaturization and high integration, although a total chip area increases in proportion to the increase of memory capacity, a cell area where patterns of semiconductor devices are formed is substantially reduced. Since as many patterns as possible have to be formed in the limited cell area to ensure the desired memory capacity, fine patterns having a reduced critical dimension must be formed.
Thereby, a method of reducing a unit cell size has been studied. Currently, a study on a method of reducing a chip size of a dynamic random access memory (DRAM) device and increasing the number of chips per a wafer by employing a 6F2 or a 4F2 configuration instead of an 8F2 configuration has progressed.
In a 6F2 unit cell, active regions having an island type are arranged to be diagonally spaced apart, but implementation is limited due to the high integration of semiconductor devices. Thereby, a method of forming active regions having a line type, rather than an island type, has been suggested. In this configuration, active regions are patterned in a line extending in a diagonal direction and a device isolation layer is also patterned in a line type to be disposed between the active regions.
However, as a semiconductor device becomes more highly integrated, the critical dimension (CD), a minimum pattern size available under a given process condition, of a gate is becomes narrower and a channel length is reduced. This results in a short channel effect (SCE), which degrades performance of a field effect transistor (FET). So as to overcome this problem, a multi-channel FET, such as a recessed gate or a fin type gate, is used. The recessed gate is formed by forming a trench in a semiconductor substrate to a predetermined depth and filling the trench with a conductive material.
On the other hand, the fin type gate is formed in an uplifted substrate in a fin shape to increase a contact area between the active region and a gate, thereby improving gate's performance in drivability and electric characteristics.
When the above-described fin type gate is employed for a device that has a line type active region and a line type device isolation layer, a sub-threshold swing of the semiconductor device can be improved. However, as CD decreases, it becomes hard to control the gate surrounding the fin shaped substrate and thus the sub-threshold swing property is degraded.